1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more specifically, to a method for fabricating MOS transistors.
2. Description of Related Art
As the density of devices in an integrated circuit increases, a number of undesirable effects that prevent the devices from achieving normal operation have become more significant. For example, the shrinkage of channel length in a transistor device results in a hot-electron effect, which causes gate leakage current and oxide traps, thus affecting the reliability of the device. Therefore, in order to eliminate the undesirable effects and improve performance of integrated circuits, the structures and manufacturing processes of semiconductor devices have been modified when such devices are used in the fabrication of high density integrated circuits.
Among all the proposed structures of the semiconductor devices, transistors with a lightly-doped drain (LDD) structure have proven to have a good immunity from the so called "hot-electron effect". A brief description of the manufacturing processes of the LDD transistor is provided with reference to the cross-sectional views of FIG. 1A and FIG. 1B.
FIG. 1A illustrates a gate oxide layer 11 and a polysilicon gate electrode 12 that are respectively formed over a P-type silicon substrate 10 to constitute a gate structure. The gate structure is used as a mask, and an ion implantation step is performed to form lightly-doped source/drain regions 13 in silicon substrate 10. The ion implantation step can be carried out, for example, by implanting phosphorous ions into the substrate, thus forming N-type diffusion regions.
Referring to FIG. 1B, spacers 14 are formed on sidewalls of the gate structure. Then another ion implantation step is performed to form heavily-doped source/drain regions 15 in silicon substrate 10. The ion implantation step is carried out by implanting arsenic ions into the substrate through the mask of the gate structure and spacers 14, thus forming N-type heavily doped source/drain regions 15.
The structure of FIG. 1B somewhat reduces the electric field in the channel and drain regions. However, if an even smaller dimension of the transistor is required, the electric field in the above-mentioned LDD structure is again high enough to generate hot electrons. These hot electrons will induce a hot-electron effect, that is, these hot electrons will be trapped in the gate oxide or fly into the gate electrode and create a gate leakage current, thus reducing the saturation current of the transistor. Moreover, an electron-hole pair impact region will exist near the junction of the drain-substrate regions due to the high electric field thereof, thus affecting the performance of the transistor.